In semiconductor non-volatile memory arrays, word lines and bit lines are usually arranged in rows and columns, respectively, to address memory cells. Word lines and bit lines either span the entire array or large blocks of memory cells in the array. Address decoders formed of row decoders and column decoders select appropriate word lines and bit lines to program, read and erase memory cells. Bit lines are usually associated with subsurface source-drain electrodes, while word lines are usually associated with top level select gates of non-volatile memory transistors.
As non-volatile memory cell size shrinks, the smallest memory cells can have a dimension of F, the minimum feature size, or perhaps slightly larger such as 2F or 3F, when viewed in top view. As a specific dimension, F depends on lithographic equipment, but is scalable to whatever lithographic equipment is available. In modern stepper equipment, F is typically in the range of 40 to 150 nanometers and is forecast to become smaller. F depends on the wavelength of the exposing light multiplied by a resolution factor and divided by the numerical aperture of the lithographic system. The resolution factor depends on several variables in the photolithographic process including the quality of the photoresist used and the resolution enhancement techniques such as phase shift masks, off-axis illumination and optical proximity correction. In the industry, F is a characteristic of particular semiconductor manufacturing equipment that uses photolithography. For example, see U.S. Pat. No. 7,075,146 entitled A4F2 EEPROM NROM Memory Arrays with Vertical Devices by L. Forbes.
To make contact with the top level select gates of non-volatile transistors, word lines made of polysilicon are used since they can be fabricated using photolithography as lines having a width of dimension F to contact select gates in a row. Similarly, the distance between word lines can also have the dimension F. Contact is established at the outside periphery of the array or large block of the array whereby electrical signals are propagated on the word line across the array or block. The resistance of polysilicon word lines, as well as distributed capacitance, reduces access time to and from the array. In the prior art, the problem of slow memory array access time due to word line resistance has been recognized. One prior art solution is to use metal straps parallel to the polysilicon word line to lower word line resistance. For example, see U.S. Pat. No. 6,266,264 to R. Proebsting. However, it is not possible to make metal straps the same width as the ultra narrow word lines and so a problem exists in locating metal straps for small geometry memory arrays having narrow width word lines.
Another prior art approach is to stack word line straps in two metal layers with half of the polysilicon word line strapped in a first metal layer and the other half in the second metal layer. This approach has been used in several variations but does not appear suitable where word lines have the minimum feature size, F, as a width dimension.